? semiconductor components industries, llc, 2009 october, 2009 ? rev. 6 1 publication order number: mc14020b/d mc14020b 14-bit binary counter the mc14020b 14 ? stage binary counter is constructed with mos p ? channel and n ? channel enhancement mode devices in a single monolithic structure. this part is designed with an input wave shaping circuit and 14 stages of ripple ? carry binary counter. the device advances the count on the negative ? going edge of the clock pulse. applications include time delay circuits, counter controls, and frequency ? dividing circuits. features ? fully static operation ? diode protection on all inputs ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two low ? power ttl loads or one low ? power schottky ttl load over the rated temperature range ? buffered outputs available from stages 1 and 4 thru 14 ? common reset line ? pin ? for ? pin replacement for cd4020b ? these are pb ? free devices maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ? 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ? 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ? 55 to +125 c t stg storage temperature range ? 65 to +150 c t l lead temperature (8 ? second soldering) 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. http://onsemi.com marking diagrams pdip ? 16 p suffix case 648 mc14020bcp awlyywwg soic ? 16 d suffix case 751b tssop ? 16 dt suffix case 948f 14020bg awlyww a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free indicator soeiaj ? 16 f suffix case 966 mc14020b alywg see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 16 1 1 16 1 16 14 020b alyw 1 16 (note: microdot may be in either location)
mc14020b http://onsemi.com 2 truth table clock reset output state 0 no change 0 advance to next state x 1 all outputs are low x = don?t care logic diagram clock reset 11 10 q1 q4 q5 q12 q13 q14 975 123 c c r q q c c r q q c c r q q c c r q q c c r q q c c q r q6 = pin 4 q7 = pin 6 q8 = pin 13 q9 = pin 12 q10 = pin 14 q11 = pin 15 v dd = pin 16 v ss = pin 8 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 q9 q8 q10 q11 v dd q1 c r q6 q14 q13 q12 v ss q4 q7 q5 ordering information device package shipping ? mc14020bcpg pdip ? 16 (pb ? free) 500 units / rail mc14020bdg soic ? 16 (pb ? free) 48 units / rail MC14020BDR2G soic ? 16 (pb ? free) 2500 units / tape & reel mc14020bdtg tssop ? 16* 96 units / rail mc14020bfelg soeiaj ? 16 (pb ? free) 2000 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
mc14020b http://onsemi.com 3 electrical characteristics (voltages referenced to v ss ) characteristic symbol v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? level v in = v dd or 0 ?1? level v in = 0 or v dd v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i oh 5.0 5.0 10 15 ? 3.0 ? 0.64 ? 1.6 ? 4.2 ? ? ? ? ? 2.4 ? 0.51 ? 1.3 ? 3.4 ? 4.2 ? 0.88 ? 2.25 ? 8.8 ? ? ? ? ? 1.7 ? 0.36 ? 0.9 ? 2.4 ? ? ? ? madc i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc total supply current (notes 3 & 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (0.42 a/khz)f + i dd i t = (0.85 a/khz)f + i dd i t = (1.43 a/khz)f + i dd adc 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.001.
mc14020b http://onsemi.com 4 switching characteristics (note 5) (c l = 50 pf, t a = 25 c) characteristic symbol v dd vdc min typ (note 6) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time clock to q1 t phl , t plh = (1.7 ns/pf) c l + 175 ns t phl , t plh = (0.66 ns/pf) c l + 82 ns t phl , t plh = (0.5 ns/pf) c l + 55 ns t plh , t phl 5.0 10 15 ? ? ? 260 115 80 520 230 160 ns clock to q14 t phl , t plh ? (1.7 ns/pf) c l + 1735 ns t phl , t plh = (0.66 ns/pf) c l + 772 ns t phl , t plh = (0.5 ns/pf) c l + 535 ns 5.0 10 15 ? ? ? 1820 805 560 3900 1725 1200 ns propagation delay time reset to q n t phl = (1.7 ns/pf) c l + 285 ns t phl = (0.66 ns/pf) c l + 122 ns t phl = (0.5 ns/pf) c l + 90 ns t phl 5.0 10 15 ? ? ? 370 155 115 740 310 230 ns clock pulse width t wh 5.0 10 15 500 165 125 140 55 38 ? ? ? ns clock pulse frequency f max 5.0 10 15 1.0 3.0 4.0 2.0 6.0 8.0 ? ? ? mhz clock rise and fall time t tlh , t thl 5.0 10 15 no limit ? reset pulse width t wl 5.0 10 15 3000 550 420 320 120 80 ? ? ? ns reset recovery time t rec 5.0 10 15 ? ? ? 65 25 15 130 50 30 ns 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14020b http://onsemi.com 5 figure 1. power dissipation test circuit and waveform figure 2. switching time test circuit and waveforms 500 f 0.01 f ceramic pulse generator v dd c l c l c l v ss c r q1 q4 q n i d v dd v ss 20 ns 20 ns clock 90% 50% 10% 50% duty cycle pulse generator v dd v ss c r q1 q4 q n c l c l c l 20 ns 20 ns clock 90% 50% 10% t wh t plh t phl 90% 50% 10% t tlh t thl q figure 3. timing diagram clock reset q1 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 16,384 8192 4096 1 2 4 8 16 32 64 128 256 512 1024 2048
mc14020b http://onsemi.com 6 package dimensions pdip ? 16 p suffix plastic dip package case 648 ? 08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic ? 16 d suffix plastic soic package case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc14020b http://onsemi.com 7 package dimensions tssop ? 16 dt suffix plastic tssop package case 948f ? 01 issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint
mc14020b http://onsemi.com 8 package dimensions soeiaj ? 16 f suffix plastic eiaj soic package case 966 ? 01 issue a h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc14020b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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